Designing and fabricating electronic systems typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of electronic system to be manufactured, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system from a design. Typically, software and hardware “tools” verify the design at various stages of the design flow by running simulators and/or hardware emulators, or by utilizing formal techniques, allowing any errors in the design discovered during the verification process to be corrected.
Initially, a specification for a new electronic system can be transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic system. With this logical design, the electronic system can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as System Verilog or Very high speed integrated circuit Hardware Design Language (VHDL).
The logic of the electronic system can be analyzed to confirm that it will accurately perform the functions desired for the electronic system, sometimes referred to as “functional verification.” A design verification tool can perform functional verification operations, such as simulating, emulating, and/or formally verifying the logical design. For example, when the design verification tool simulates the logical design, the design verification tool can provide transactions or sets of test vectors, for example, generated by a simulated test bench, to the simulated logical design. The design verification tool can determine how the simulated logical design responded to the transactions or test vectors, and verify, from that response, that the logical design describes circuitry to accurately perform functions.
The design verification tool also can quantify how well the test vectors input to a logical design under verification came to covering or adequately exercising the logical design. Traditional techniques to determine coverage of the logical design include code coverage and functional coverage. Code coverage, such as statement coverage, branch coverage, decision coverage, condition coverage, expression coverage, toggle coverage, or the like, can identify which lines, statements, expressions, decisions, or toggles of the logical design were exercised by the test bench during verification operations. Functional coverage can quantify how well the logical design had its functionality exercised during verification operations.
Functional coverage has gained widespread popularity among verification engineers due to its ability to allow the engineers to focus on aspects of system level design, such as coverage of a covergroup. The covergroup can define multiple coverpoints, such as particular signal states or particular variable values occurring during verification operations, and define coverage crosses, such as a plurality of the coverpoints in the covergroup occurring at the same time. The design verification tool can quantify coverage for the covergroup and, for example, report a list of the coverpoints and the coverage crosses that contribute to coverage of the covergroup.
Verification engineers seeking to increase coverage of the covergroup typically utilize the list to ascertain uncovered or lightly covered coverpoints and coverage crosses and then develop new test vectors that attempt to cover some of those coverpoints and coverage crosses. The decision on which of the uncovered or lightly covered coverpoints and coverage crosses to target with the new test vectors remains dependent on intuition of the verification engineers. This process can iterate until the verification engineers have generated enough sets of test vectors to achieve coverage closure for the covergroup.